1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, in particular, to integrated circuits including ferroelectric memory.
2. Description of the Related Art Integrated circuits typically include a large number of circuit elements, which form an electric circuit. The circuit elements in an integrated circuit may be electrically connected by means of electrically conductive metal lines formed in an interlayer dielectric material. The electrically conductive metal lines may be provided in a plurality of interconnect layers that are stacked on top of each other above a substrate in and on which circuit elements, such as field effect transistors and other circuit elements such as capacitors, diodes and resistors, are formed. Metal lines in different interconnect layers may be electrically connected with each other by means of contact vias that are filled with metal.
Integrated circuits may include nonvolatile memory. In some types of nonvolatile memory, ferroelectric materials may be employed. Ferroelectric materials can maintain an electric polarization in the absence of an external electrical field. Different directions of the electrical polarization of a small amount of ferroelectric material which may be provided, for example, in a gate structure of a field effect transistor or between the electrodes of a capacitor may be used to represent a bit of information, wherein a first polarization direction is identified with a logical 0, and a second polarization direction is identified with a logical 1.
U.S. Pat. No. 5,877,977 discloses a type of nonvolatile memory that is based on a metal-ferroelectric-metal-insulator-semiconductor field effect transistor (MFMIS-FET) structure. The MFMIS-FET structure includes a source region, a channel region and a drain region. Above the channel region, a ferroelectric layer arranged between upper and lower electrodes and a silicon oxynitride gate insulation layer are provided. The gate insulation layer is arranged between the channel region and the lower electrode. Thus, an arrangement that is electrically analogous to two capacitors in series is provided. A first capacitor is provided by the upper and lower electrodes, with the ferroelectric layer arranged as a capacitor dielectric therebetween, and a second capacitor is provided by the channel region and the lower electrode as capacitor electrodes, with the gate insulation layer arranged therebetween as a capacitor dielectric.
When a bias voltage is applied to the upper electrode, a remanent polarization of the ferroelectric layer may be obtained, wherein the direction of the remanent polarization depends on whether the bias voltage is positive or negative. The direction of the remanent polarization may be identified with the value of a bit stored in the MFMIS-FET.
The remanent polarization of the ferroelectric layer may have an influence on the electrical conductivity of the channel region that is obtained in the absence of a bias voltage applied to the upper electrode. Therefore, the bit of information stored in the MFMIS-FET device may be read by sensing whether the MFMIS-FET is in an “ON” state or in an “OFF” state when no bias voltage is applied to the upper electrode.
The applicability of an MFMIS-FET structure as described above may depend on a ratio between a capacitance of the first capacitor formed by the upper and lower electrodes and the ferroelectric layer, and the second capacitor formed by the lower electrode, the gate insulation layer and the channel region. A relatively small capacitance of the first capacitor as compared to the capacitance of the second capacitor may have the advantage of reducing the bias voltage that needs to be applied between the upper electrode and the channel region for applying a particular external electric field to the ferroelectric layer. However, the possibilities of tuning the thicknesses and dielectric constants of the ferroelectric layer and the gate insulation layer may be limited.
Embodiments of the present disclosure provide devices that address this issue and methods for the formation of such devices.